Memory storage capacities of embedded EEPROM memories used in smart card applications are being made ever larger to meet increasing memory requirements. One issue that arises with large memories is the ability to control the programming quality of the memories' bit cells, typically of the floating-gate type in EEPROMs. In existing systems, programming of an EEPROM has two phases. In a first ‘load’ phase, the data to be programmed are loaded from a RAM memory through a data input bus into column latch circuits of the EEPROM. Typically, the minimum data size that can be loaded is one byte and the maximum is a row or page of 64 or 128 bytes. In a second ‘write’ phase, the data stored in the column latches are transferred into addressed bit cells in the EEPROM memory array. The column latch circuits only serve to store the data while the programming of the bit cells is taking place. In order to verify the programming quality, the data is then read from the EEPROM's programmed bit cells and compared with the original data already stored in the RAM. If the data read out from the cells differs from the original data, programming of erroneous bytes is repeated until the correct data are verified.
A typical existing program column latch circuit has a low voltage portion and a high voltage portion. The low voltage portion is a simple latch (cross-coupled inverters) to which input data are written through a first transmission gate during the load phase of the programming operation. The high voltage portion is a level shifter supplied with the high voltage needed for programming. During the write phase of the programming operation, data stored in the low voltage latch are transferred into the high voltage portion through a second transmission gate that separates the low and high voltage portions. The level shifter pulls a ‘1’ data value up to the programming voltage, while a ‘0’ data value remains at 0V. The resulting voltage level in the level shifter controls a third transmission gate that drives one column of the memory cell array via a bit line. The voltage at the terminal opposite from the bit line is at the programming voltage for writing and at 0V for erasing. For verifying, the memory cells are read out through their normal read paths via sense amplifiers attached to the bit lines at the end opposite from the program column latches.